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RISC-V single-cycle processor using Verilog: A tutorial on building a RISC-V microprocessor for an FPGA using Verilog
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Product Details
- A tutorial on creating a basic single-cycle Harvard architecture RISC-V RV32I processor in Verilog to be run on an FPGA (tested Altera DE2 or Digilent Nexys 4 DDR).Starting with a simple implementation of a program counter, this tutorial builds to a complete RV32I implementation including memory mapped input / output and misaligned load and store handling.Contains the complete Verilog code (which is also freely available on github)Not a tutorial on Verilog, FPGAs or digital design generally.It assumes familiarity with these topics and also FPGA toolsets such as Vivadao and Quartus.
| Publisher | Independently published |
| Publication date | 24 Feb. 2026 |
| Language | English |
| Print length | 284 pages |
| ISBN-13 | 979-8249151010 |
| Item weight | 494 g |
| Dimensions | 15.84 x 2.11 x 23.46 cm |
Product Description
RISC-V single-cycle processor using Verilog: A tutorial on building a RISC-V microprocessor for an FPGA using Verilog
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